* Building a test bench, creating test vectors, and running the verification environment to verify that the subsystem you designed works properly
* Synthesize the subsystem into logic and perform Static Timing Analysis (STA) on the design to make sure it meets the timing requirements
* Designing, integrating, and verifying a system fabric bus into a subsystem
Minimum Qualifications
Digital Logic Design knowledge
Verilog/System Verilog RTL language design entry
Synopsys/Cadence synthesis
Synopsys PrimeTime Static Timing Analysis (STA)
Synopsys (VCS)/Cadence(Incisive) simulation
Strong problem solving and analytical skills
Strong communication skills combined with team-oriented approaches to own the verification efforts in a specific area of the design
Preferred Qualifications
* Experience/exposure writing specifications and documentation
* Experience/exposure with verifying logic design hardware
* Experience/exposure to front-end tools and methodologies