Specify, design, and help in the verification and lab bring-up of advanced mixed-signal circuits (digital side)
Minimum Qualifications
Knowledge of mixed signal concepts
Knowledge of RTL design
Knowledge of Verilog and SystemVerilog
Knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
Good communication and presentation skills
Preferred Qualifications
Master´s degree or PhD in Electrical/Computer Engineering or proven industrial experience/degree equivalent
Good knowledge of scripting languages. Perl and Python are plusses
Good knowledge of synthesis, static timing, DFT, is a plus
Good knowledge of SystemVerilog assertions, checkers, and other design verification techniques are a plus