CPU DFT Verification Engineer

As a CPU DFT Verification Engineer, you will have the following responsibilities:

• Work closely with architecture, RTL designers, and DFT designers on verifying the functionality correctness of the DFT logic
• Execute test plans for DFT logic
• Develop testbenches and tests according to test plans
• Debug simulation failures
• Develop coverage monitors and analyze coverage to ensure all test cases in the plans are covered
• Develop Verilog checkers or assertions to verify the design
• Work with the silicon bringup team on developing tests that help the silicon bring up effort

Minimum Qualifications
Minimum BS
Academic experience in computer architecture
Academic experience in digital design using Verilog

Preferred Qualifications
Master’s degree preferred
Knowledge of DFT and structural debug concepts and methodologies: JTAG, MBIST and scan
Knowledge of digital logic design, debug feature, and DFT architecture and microarchitecture
Proficiency in programming and scripting in Python, Perl, or TCL
Experience or academic knowledge in design verification methodology. Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkers
Good understanding of CPU architecture is a plus
Should be an extraordinary teammate with excellent communication skills with the ability to articulate complex design issues during verification effort
Be able to follow detailed work schedules and work independently on the verification efforts for a block/area of the design