Wireless SOC Verification Engineer

You will learn all aspects of a large-scale SOC, different types of SOC architectures, high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of multi-chip SOC debug architecture. As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing state of the art Wireless SOCs. This position comes with responsibility for pre-silicon RTL verification of block and top-level SOC, all aspects of SOC Design Verification engineering, and will enable you to thrive in a dynamic multi-functional organization, debate ideas openly, and deliver on complex Wireless protocol chip requirements.

Minimum Qualifications
BS and a minimum of 10 years relevant industry experience.
Proven track record of working full ASIC cycle from concept to tape-out to bring-up, including test-planning, testbench implementation, test sequence creation and debugging, and coverage closure.
Expertise in SystemVerilog coding and UVM methodology

Preferred Qualifications
Dedicated/hands-on ASIC & SOC DV experience.
Experience taping out large SOC systems with embedded processor cores.
Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
Experience with Formal Verification.
In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification.
Low Power Verification experience.
Should be a great teammate with excellent communication and problem-solving skills and the desire to seek diverse challenges.