Validate CPU cores, cache coherency, and memory hierarchy behavior on post-silicon platforms.
Develop targeted stress tests to expose incorrect behavior under varying operating conditions(voltage, frequency, and temperature).
Partner with design and architecture teams to correlate silicon behavior with intended micro architectural design.
Catch incorrect silicon behavior and issues before product release.
Identify sensitivity to PVT shifts, including incorrect behaviors and intermittent failures.
Collect and analyze silicon data (logs, counters, traces) to understand system behavior across operating conditions.
Provide actionable feedback to PVT and other teams to refine operating limits

Minimum Qualifications
BS in Computer Science, Electrical Engineering, Computer Engineering, or related field with a minimum of 3 years relevant industry experience.
Experience in post-silicon validation, PVT, system bring-up, or silicon debug.

Preferred Qualifications
Strong understanding of CPU microarchitecture, cache coherency, and memory hierarchy.
Knowledge of SoC-level power, clocking, and voltage domains.
Experience working with PVT, reliability, or silicon characterization teams.
Proficiency in C/C++ and scripting (Python) for automation and analysis.
Hands-on experience debugging real silicon across voltage, frequency, and temperature corners.
Ability to communicate complex silicon issues clearly to cross-functional partners.