Work with our design, verification and integration engineers to ensure memory controller and PHY requirements are well defined and cover the scope of DRAM based corner cases.
Collaborate with Architecture, MCU, DDRPHY and DRAM vendors for Apple’s main memory feature.
Ensure DRAM simulation meets Apple's requirements.
Ensure the internal and external DRAM silicon and package level testing needs are met.
Debug RMA material with apparent DRAM related defects.

Minimum Qualifications
MS or BS Degree with 4+ years in DRAM development

Preferred Qualifications
Expert in DRAM cell architectures
Expert of DRAM memory organization and periphery design for low DRAM power
Expertise in DRAM simulation
Experience in memory interface verification with understanding DDR-PHY and Memory Controller
Experience in LPDDR IO (DDR/DDR2/DDR3/DDR4/DDR5) characterization and qualification
Understanding of memory test patterns
Knowledge of DRAM reliability
Knowledge with innovative packaging technology (POP, TSV, etc.) and their relationship to DRAM signal/power integrity
Previous experience in Failure Analysis of DRAM devices
Excellent hardware and software debug skill
Experience working with the major DRAM vendors
Strong background in computer architecture
Programming experience in C/C++
Excellent interpersonal skills and teamwork.