CPU DFT Verification Engineer

As a CPU DFT Verification Engineer, you will have the following responsibilities:

• Work closely with architecture, RTL designers, and DFT designers on verifying the functionality correctness of the DFT logic
• Execute test plans for DFT logic
• Develop testbenches and tests according to test plans
• Debug simulation failures
• Develop coverage monitors and analyze coverage to ensure all test cases in the plans are covered
• Develop Verilog checkers or assertions to verify the design
• Work with the silicon bringup team on developing tests that help the silicon bring up effort

Minimum Qualifications
Minimum BS and 3+ years of relevant industry experience
Experience in DFT design, DFT verification, or processor verification
Experience with digital logic design, test/debug feature, or DFT architecture
Experience with DFT and structural debug concepts and methodologies: JTAG, IEEE1500, or MBIST and scan
Experience in scripting in Python, Perl, or TCL

Preferred Qualifications
Master’s degree preferred
Understanding of CPU architecture
Experience in developing design verification test plans, test benches, and test vectors generation
Experience with lab debug of CPUs/ASIC using built-in DFT and debug features is a plus
In-depth knowledge in design verification environments like random constraint verification
Knowledge of Verilog and experience with simulators and waveform debugging tools
Should be an extraordinary teammate with excellent communication skills with the ability to articulate complex design issues during verification effort
Be able to create and follow detailed work schedule and work independently on the verification efforts for a block/area of the design