Candidates will be responsible for PPA optimization of the netlist, working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition and be involved in understanding and improving our current methodologies. Through this collaboration, you will deliver the best-in-class GPU’s for the best consumer products. If you’re ready to help chart the future of Apple Silicon, we’d love to talk to you.

Minimum Qualifications
Experience with physical synthesis, including logic and PPA optimization techniques
Experience with Verilog, System Verilog or other scripting languages
Experience using logic equivalence tools for RTL and Gate-level designs
BS + 3 years of relevant experience

Preferred Qualifications
Understanding and application of physical design (PD) and static timing analysis (STA) principles
Ability to analyze critical paths and guide RTL designs to optimal solutions
Collaborate effectively with IP teams spanning multiple sites
Familiarity with DFT insertion
Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts across RTL and Gate-Level
Experience implementing ECOs for functionality and timing