As a member of SOC emulation team candidate will be involved in:
-Support multiple Emulation environments using the latest emulation techniques:- C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, Accelerated UVM Testbenches.
-SoC bringup on emulation, root cause failing SoC/Processor tests and emulator environment issues
-Strong design, debug, communication and teamwork skills are essential
-Work with the leading emulation vendors to debug issues.
-This role requires close collaboration with Design, DV, Power, Silicon Validation, Performance and Software teams.

Minimum Qualifications
Bachelor's degree and a minimum of 3 years relevant industry experience

Preferred Qualifications
Experience with Verilog, VHDL design
Experience with C/C++ and System Verilog, Design Verification environments
Experience with waveform debug tools
Experience in writing Synthesize-able SystemVerilog/Verilog code and SystemVerilog assertions
Experience on any Scripting (Perl/Python/TCL/Makefile)
Excellent analytical and debug skills
Emulation experience on available platforms-Palladium, Veloce, or Zebu, including compilation, debug, performance and throughput tuning is a strong plus
Experience with Serial/High-Speed Protocols (PCIE, USB, Display, CIO), UVM Acceleration is plus.
Strong communication skills and ability to work as a team.