As an experienced CAD engineer, you will assist with delivering high quality infrastructure for automating chip design processes. Specifically as the chip designs are becoming larger than ever, there is a growing need to optimise the performance of simulation tools to maximise the efficiency and reduce resource requirements (both in compute time and space). The scope of work includes developing and deploying new methodologies with vendor and internal teams, supporting and debugging issues on large scale simulations.

Minimum Qualifications
BS, MS, or PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, Computer Science, Software Engineering or a related field
Minimum 5 years of experience working on RTL simulation tools
Strong foundation on Linux and grid computing systems
Knowledge of scripting languages such as Python or Perl
Strong interpersonal and analytical skills
Ability to work well within a team and be productive under tight schedules
Fluency in English required

Preferred Qualifications
Expert knowledge on Cadence tool chain
Familiarity with SystemVerilog / Verilog / VHDL
A curiosity about GPU / PMU / CPU / SOC architecture and micro-architecture