CAD Engineer - Timing for Gate-Level Flows & Methodologies

As a member of our STA CAD team, you will:

• Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs
• Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure
• Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlation
• Develop and maintain scripts and methods for timing analysis and power reduction
• Develop and support methodologies, tools, and flows used in the verification of timing constraints, drive best practices across design teams
• Analysis of timing paths to identify key issues, including post-silicon timing debug
• Work closely with EDA vendors to develop and incorporate new capabilities to solve technical problems

Minimum Qualifications
Minimum requirement of BS and 3 years of relevant industry experience.

Preferred Qualifications
Experience with static timing analysis tools and flows
Understanding of programming fundamentals and concepts. Familiarity with Python and Tcl or other high level programming languages
Familiar with STA of large high-performance SoC designs in deep sub-micron technologies
Understanding of fundamentals in noise, cross-talk, variation and timing margins
Knowledge of timing/SDC constraints, hands on experience in creation/validation a plus
Good communicator who can accurately assess and describe issues to management as well as follow solutions through to completion