As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC Timing: Full chip and block level timing closure/constraints ownership throughout the entire project. You will be working with other specialists that are members of the SoC Design, SoC Design Verification, DFT, Architecture and Physical Design teams. Working with CAD and Flow teams to define and improve front-end design methodologies. Develop and maintain methodology and flows related to timing analysis.

Minimum Qualifications
Bachelors Degree + 0 Years of Experience.

Preferred Qualifications
Strong fundamentals in the area of Digital design
Familiarity with ASIC design timing concepts
Proficient in scripting languages (TCL, Python and Perl)
Exposure to STA tools (Primetime) , writing timing constraints and knowledge of timing corners / modes is a plus
Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks
Self-starter and highly motivated
Ability to communicate optimally across all internal groups