In this highly visible role, your primary responsibilities will include:
Solving issues related to transistor level simulations on Analog, RF and Microwave applications with Spice simulators on command-line and Virtuoso environment.
Guide and assist designers in solving tool issues related to Analog Design Environment (ADE/XL, Maestro, OCEAN etc.) and develop automation flows.
Contribute to methodology on SPICE simulation and modeling techniques related to circuits, thereby influencing the advancement of a variety of technology nodes.
Develop next generation in-house EDA CAD flow solutions related to Analog and Mixed-signal simulations.
Minimum Qualifications
Experience in SPICE simulation and design environment to handle flow/tool issues in Analog/RF circuit domain.
Programming/scripting skills in Perl, Python, SKILL language, or Shell.
Good written and verbal communication skills, and the ability to collaborate well with cross-functional teams.
Minimum requirement of BS degree and 3+ years of relevant industry experience
Preferred Qualifications
Domain experience in circuit simulations with Analog/RFIC design and/or related CAD/automation support areas involving various technology nodes and tape out.
Exposure to Cadence ADE environment including knowledge of Virtuoso Schematic Editor, PDK, CDF, Callbacks, Netlisting, Virtuoso Analog Design Environment (ADE-L/XL/GXL/Maestro), OCEAN tools.
Knowledge of SPICE simulators, including Spectre, Spectre RF, Solido/AFS, Hspice, ADS, GoldenGate, AMS Designer, XA, Hsim, and FineSim.
Ability to solve simulation accuracy, speed and capacity issues. Knowledge of AC, DC, Tran, Harmonic Balance, S-parameters, Periodic noise, PSS simulations.
Experience in device level SOA checks, ERC asserts, statistical simulations using Monte Carlo, PVT and Reliability/aging analysis involving Self-Heating is a plus.
Experience in evaluating simulation and environment related CAD tool/product applications and driving EDA vendors to meet design requirements.
Understand custom IC designs, and knowledge of Post-layout DSPF/SPF extraction. Knowledge of behavioral RTL/AMS circuits, experience in Verilog- A/AMS. Knowledge of PDK and spice models qualification.
Programming skills in SKILL language, Python, Perl, or Shell. Ability to provide automations for rapid and dynamic design needs. Knowledge in Perforce and/or regressions is preferred.