Core Responsibilities:

Develop and document micro architecture from high level architectural descriptions
Deliver high quality design collateral, including RTL, to Physical Design teams
Specify clock, power, and interface descriptions to ensure optimized design
Assess and integrate IP from other Apple teams
Close timing, power, area, and lint for design by optimizing RTL and constraints
Drive performance, power, area, and functional goals
Provide schedules to IP teams and management
Lead project milestones for on time delivery
Collaborate effectively with IP teams spanning multiple sites

Minimum Qualifications
BS + 10 years of relevant experience
Experience in one or more of the following: logic optimization, synthesis, timing analysis, floor-planning, power intent descriptions, and clock domain clock crossings
Experience with logic simulation and debug
Experience in power management with CPUs, GPUs, or SOCs

Preferred Qualifications
Ability to write one or more scripting languages
Experience in Graphics hardware design
Ability to write RTL in Verilog and/or System Verilog that meets timing, power, and performance goals
Expertise in CDC, RDC, and UPF collateral
Leadership experience with driving project milestones to completion