CPU Gate Level Synthesis Engineer

As a CPU Gate Level Synthesis Engineer, you will drive the early-stage development of high-performance, low-power digital designs for cutting-edge high-performance CPUs. This role involves running RTL to gate level synthesis and finding opportunities to optimize timing, power, and area for micro-architectural features. You will collaborate with cross-functional teams to implement synthesis methodologies, constraint development, DFT integration, RTL optimization and power analysis. Responsibilities include but are not limited to:

• Early RTL health assessment to detect potential timing/gate-depth issues and collaborating with the RTL & physical design teams in exploring solutions
• Early stage power estimation and validation for new micro-architectural features
• Enhancing synthesis flows for good correlation to post-route to ensure high fidelity of synthesis-based feedback
• Work closely with DFT teams to ensure seamless integration of scan chain, ATPG, and MBIST into the synthesis flow
• Partner with timing team to enable constraints generation at top levels
• Debug and resolve timing, power, and area issues, ensuring efficient and scalable designs
• Track and analyze PPA trends through project cycle

Minimum Qualifications
Minimum BS and 3+ years of relevant industry experience
Experience in digital logic design, RTL synthesis, and physical design

Preferred Qualifications
The ideal candidate should ideally possess CPU implementation experience
Proficiency in scripting languages (TCL, Perl, Python) for automation and flow optimization
Strong problem-solving, debugging, and collaboration skills in a fast-paced environment