As a RTL Engineer, you will participate in the following:

• Microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification
• RTL feature ownership – development, assessment and refinement of new RTL features to target power, performance, area and timing goals
• Validation - support test bench development and simulation for functional and performance verification
• Performance exploration and correlation - explore high performance strategies and validate that the RTL design meets targeted performance
• Design delivery - work with multifunctional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability, and power

Minimum Qualifications
Minimum BS
Experience with either Verilog or VHDL

Preferred Qualifications
Experience with microprocessor architecture
Experience with simulators and waveform debugging tools such as Verdi
Knowledge of logic design principles
Understanding of timing, power and area tradeoffs in CPU microarchitecture
Understanding of low power and high performance microarchitecture techniques
Experience using an interpretive language such as Perl or Python