Design and develop hardware for cache subsystem in high performance system on a chip (SoC).
Develop cache micro-architecture based on architecture guidelines and model analysis.
Explore architecture trade-offs in system performance, area, and power consumption.
Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem.
Work on front-end netlist and area/timing analysis of the cache subsystem.
Work with physical design team on the timing closure of the cache subsystem.

Minimum Qualifications
10 + years of full time ASIC design experience
memory system development
RTL/micro-architecture definition
PPA (performance/power/area) analysis
Cache design background including an understanding of different memory organizations and tradeoffs.
Hands on Experience with multi-processor cache coherence protocols
B.S. in a relevant field

Preferred Qualifications
Knowledge of high-performance coherent memory systems or interconnect architectures
Knowledge of high-performance DRAM controller
M.S in a relevant field.