Work in a cross-functional team that delivers high quality on-chip IPs immune to ESD/EOS and latchup events. Ensure ESD robust designs with minimum cost to mission-mode functions.
Minimum Qualifications
BS degree in technical discipline with years of relevant experience.
Preferred Qualifications
MS degree, preferred
Deep understanding of transistor device characteristics
Solid understanding of models used for testing ESD, including HBM, CDM, MM and IEC-61000-4-2
Knowledge of state-of-the-art ESD circuit design techniques and topologies
Hands-on experience with design/layout EDA tools, including Virtuoso, Calibre, Allegro, etc.
Experience with ESD/LUP test and characterization equipment
Strong initiative, collaboration, and ownership of responsibilities, productive, able to meet challenging deadlines
Excellent written and verbal communication skills