You will learn all aspects of a large-scale SOC, different types of SOC architectures, high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of multi-chip SOC debug architecture. As a Design Verification Engineer on our team, you’ll be at the center of the verification effort within our silicon design group responsible for crafting and productizing state of the art Wireless SOCs. This position comes with responsibility for pre-silicon RTL verification of block and top-level SOC, all aspects of SOC Design Verification engineering, and will enable you to thrive in a dynamic multi-functional organization, debate ideas openly, and deliver on complex Wireless protocol chip requirements.

Minimum Qualifications
Minimum requirement of a bachelor’s degree
Experience with System Verilog, Verilog or UVM
Strong problem solving and analytical skills

Preferred Qualifications
Expertise in SystemVerilog coding and UVM methodology
Dedicated/hands-on ASIC & SOC DV experience
Experience with Formal Verification
Low Power Verification experience