In this role, the key responsibilities are the following:
Ownership of SerDes system bring-up, validation and debug. This will involve a SerDes bring up in system environment, verifying basic operations, analyzing robustness and margins in system.
Work with design teams to understand the architecture and define DFT needs to help enhance testability and first-time silicon success.
Be involved in mixed-signal verification tasks to better understand the SerDes operation and interaction with higher level control logic.
Minimum Qualifications
Minimum requirement of a bachelors degree.
Preferred Qualifications
The ideal candidate should have experience in high-speed serial links with expertise in the following:
Solid understanding and experience of designing analog mixed signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters.
Solid understanding of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques.
Solid understanding and experience with digitally assisted analog design concepts (e.g. background calibrations, LMS based adaptive loops).
Hands-on experience to drive lab and production testing, debug, and data analysis
Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization.
Skills in scripting and automation to enhance efficiency are highly desirable.
Experience in high-speed serial links, with knowledge of common high-speed SerDes protocols like PCIe, USB, DP, and MPHY.
Knowledge of Tx/Rx equalization techniques and circuits, including CTLE, DFE, and de-emphasis, as well as CDR architectures and implementations.
Knowledge of common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY) is highly desired.
Exposure to firmware assisted mixed signal IP development is desirable.
Knowledge and inquisitiveness in AI/ML domains, and ability to apply the concepts for improved silicon performance, and also for productivity improvements in the design/validation of the IP