Define comprehensive property sets for functional coverage of hardware models
Formalize verification properties using SVA
Execute formal proofs and analyze convergence behavior (accuracy VS execution time)
Document methodology and best practices for the verification flow
Minimum Qualifications
Currently enrolled in Computer Science or equivalent
Knowledge of formal verification techniques
Knowledge of Verilog and/or VHDL
Passionate about mathematics, and good mathematical/analytical sense
Scripting language knowledge (perl/python)
Good written and verbal communication skills
Experience in working with international teams
Preferred Qualifications
Master's / Bachelor's in Computer Science or equivalent
You are available for 6 months or more