In this role, you will perform timing analysis on custom design circuits, delivery timing views to integration teams, as well as develop custom logic design in analog/mixed-signal circuits. You will work closely with custom design engineers, and cross-functional teams at the silicon and module levels.
Minimum Qualifications
Minimum requirement of a bachelors degree.
Solid understanding of timing analysis concepts such as setup/hold time calculation, POCV on timing paths, timing constraints, transistor-level delay characterization, rise/fall time balancing, etc.
Experience of timing analysis and verification in high-speed design such as SerDes and ADC.
In-depth knowledge and analytical understanding of mixed-signal design techniques.
Strong track record of delivering silicon IPs with design and verification.
Proficiency in circuit modeling and simulation, including SPICE models and worst-case corner selection.
Preferred Qualifications
Master’s Degree with 3+ years of relevant industry experience.
Experience with STA tools such as NanoTime, PrimeTime, or Tempus.
Experience in analog/mixed-signal circuit design from architecture to fundamental implementation.
Experience in SRAM design.
Experience in timing / SDC constraints generation and management.
Good understanding of tool algorithms for noise glitch, cross-talk delay, and margining with POCV.
Proficiency in scripting languages (Python, Tcl or Perl).