As a member of our CAD team, you will architect, develop, maintain and improve physical design verification (PDV) flows. The role requires you to work on flow and run-set development for various technology nodes and tool sets. Working alongside the CAD team, you will be collaborating with the custom digital/analog/mixed-signal design, physical design (PD) and chip integration teams. You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modify existing ones. Also, you should have worked with Dummy Metal Fill generation and Design for Manufacturability (DFM) rules at different technologies.
Minimum Qualifications
Educatio: Minimum requirement of BS + 8 years of relevant industry experience
Key qualifications
Requires experience in Silicon chip design flows, including place-and-route (PnR) implementation flows
Expertise in Calibre/ICV runset coding for DRC/LVS/ERC/MFILL is required. Rule coding in PERC is a plus
Tapeout support and SoC chip-level PDV debug experience in various technology nodes is desirable
Hands-on experience with PnR tools and physical implementation flow is preferred
Knowledge/scripting in programming languages such as Perl, Python, Tcl, Shell, Makefile and/or C++
Deep understanding of Silicon technology and experience with flow development in advanced nodes
Preferred Qualifications
Knowledge of parasitic extraction and Virtuoso SKILL coding is a plus