Ownership of SerDes system bring-up, validation and debug. This will involve a SerDes bring up in system environment, verifying basic operations, analyzing robustness and margins in system.
Work with design teams to understand the architecture and define DFT needs to help enhance testability and first-time silicon success.
Be involved in mixed-signal verification tasks to better understand the SerDes operation and interaction with higher level control logic.
Minimum Qualifications
Minimum requirement of a bachelors degree.
Preferred Qualifications
Able to think outside of the box and come up with creative solutions for system validation.
Knowledge of system level considerations e.g. ESD requirements.
Very knowledgeable about and experienced with common high-speed SerDes protocols (e.g., PCIe, USB, UCIe, OIF, etc.).
Experience with system bring-up of high-speed serial links, lab testing, and defining equipment needs.
Very knowledgeable in scripting (e.g. python, C, Matlab) for automation of validation efforts.
Experience with system level S/W setup.
Experience in mixed-signal circuit pre-silicon verification and ability to closely work with circuit design team.
Knowledge of DFT to aid in the system validation.
Experience in leading mixed-signal SerDes system validation.
Experience with silicon bring-up, debug and production ramp.
Knowledge of SerDes design and architecture including CDR and equalization.
Knowledge of with Tx/Rx equalization techniques and adaptation.
Knowledge of link jitter budget for high-speed serial links and key block level requirements.
Knowledge of ADC based links and equalization techniques.
Familiarity with PCB design and specifications.
Strong communication, teamwork and problem-solving skills.
Proven track record of delivering under difficult debug and validation scenarios.