Candidates will be responsible for PPA optimisation of the netlist, working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition and be involved in understanding and improving our current methodologies. Through this collaboration, you will deliver the outstanding GPUs for the best consumer products.
If you’re ready to help chart the future of Apple Silicon, we would love to talk to you.
Minimum Qualifications
Minimum of BSc in EE.
Proficient in Verilog and/or System Verilog and scripting languages.
Experience with physical synthesis, including logic and PPA optimisation techniques.
Preferred Qualifications
Understanding and application of physical design and static timing analysis principles.
Familiarity with DFT insertion.
Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts across RTL and Gate-Level.
Experience implementing ECO's for functionality and timing.
Ability to analyze critical paths and guide RTL designs to efficient solutions.
Experience using logic equivalence tools for RTL and Gate-level designs.
Collaborate optimally with IP teams spanning multiple sites.