We bring together the brightest quantum engineers, integrated circuit (IC) engineers, quantum computing theoreticians, and software engineers to create a unique, world-leading team, working closely together to maximize our combined expertise. Our collaborative and interdisciplinary culture is an ideal fit for anyone who thrives in a cutting-edge research and development environment focused on tackling big challenges and contributing to the development of scalable quantum computers based on silicon technology.
Our team of 100+ is based across London, Sydney, San Sebastian & Maryland (US) with our main hub in our Islington lab. The primary function of this position will be to architect, build, and maintain our custom process design kits (PDKs) and physical verification enablements. In this role, you will sit within the IC Design team, serving as the critical bridge between foundry technologies, custom cryogenic silicon devices, and our circuit design group.
You will create custom PDK components from scratch and enable novel silicon spin-qubit and cryo-CMOS circuit design methodologies. No prior background in quantum physics is required.
- Development of custom PDK elements from scratch, including Schematic symbols, Layout SKILL PCells, and custom DRC and LVS decks.
- Development, qualification, and maintenance of custom Calibre SVRF rule decks tailored for non-standard layout constraints and cryogenic CMOS layout considerations.
- Integrate tier-1 foundry PDKs into Cadence Virtuoso, creating customized library extensions, layer maps, and device callbacks.
- Work closely with IC designers and layout engineers to establish best practices for physical verification and layout automation.
- Document own work for peer review and evaluate the layout and enablement work of other team members.
- Industry degree qualification in Electronic Engineering, IC Layout, Computer Science, or a related physical science/engineering field.
- 5+ years of hands-on industry experience in IC PDK Development and PDK enablement flow management.
- Demonstrated proficiency in Cadence SKILL PCell coding and Virtuoso PDK customization.
- Demonstrated proficiency in Siemens Calibre Physical Verification tools and SVRF Rule writing (specifically for DRC and LVS decks).
- Proven hands-on experience in complex DRC and LVS error debugging within analog/mixed-signal or custom digital layout environments.
- Strong analytical and problem-solving skills with a high level of self-management, self-motivation, and willingness to engage actively in peer code and layout reviews.
- Excellent verbal and written communication skills to collaborate effectively across multidisciplinary physics and IC engineering teams.
- Demonstrated experience with advanced deep-submicron CMOS nodes (40nm, 28nm, or below), including familiarity with layout-dependent effects (LOD, WPE, OSE, etc.).
- Expert knowledge of the Cadence Virtuoso Design Environment and Cadence SKILL / SKILL++ programming.
- Expert knowledge of the Siemens Calibre Physical Verification Environment.
- Familiarity with MOSFET device modeling integration (e.g., BSIM, Verilog-A) or cryogenic device enablement.
- General awareness or curiosity regarding semiconductor quantum dots or silicon spin qubit fundamentals.
- Be part of a creative, world-leading team
- Competitive salary and share options scheme
- Contributory pension scheme
- Private Medical Insurance
- Life Assurance
- Cycle-to-work Scheme
- Flexible working
- Central London location (Islington)