As chip sizes continue to grow, power efficiency(token per watt/dollar) has become critical across all NVIDIA products - from data centers to automotive and personal computing. Our PMU IP, developed over the past 17 years, is essential in optimizing chip performance and efficiency in both idle and active scenarios. The PMU IP consists of a RISC-V core and custom-designed lower power/active power/thermal control logic. It collects and processes temperature, power, VR, and idle telemetries from the entire chip. It works with software on the RISC-V core to determine efficient operating points for different workloads on different chips. We are seeking an ASIC Engineer who can help RTL coding or even architecting the next generation PMU for datacenter, GeForce, Auto, PC, Networking chips, etc.

What you’ll be doing:

Implement the micro-architecture to RTL design.
Handling the general chip sign off checklist for every milestone
Involve into the discussion with the architecture member or even the SW member for the motivation

What we need to see:

BS / MS in electrical / Microelectronics/ Integrated Circuits engineering.
Strong communication skills and proficient oral English since this role require frequent communication with external teams mainly in USA and India.
Familiar with frontend ASIC design.

Ways to stand out from the crowd:

Experience on thermal management/active power/low power design. For example, NAFLL ADC, AVFS, DVFS, PG/RG/CG, etc.
Play similar role in other system-level control features if not power related.