- Coordinate New Product Introduction activities for analog IC devices.
- Define milestones, communicate the product development schedule, and drive execution on a regular cadence.
- Partner with Design, DFT, and Test Engineers to debug, root cause, and implement corrective actions for fault isolation.
- Perform statistical analysis on large production datasets to identify and drive yield improvements.
- Apply the latest AI and machine learning technologies for deep-dive analysis, accelerating root cause identification and quality and yield optimization.
- Work with Test Engineering on test program releases through correlation analysis.
- Define ATE characterization test plans and generate characterization reports.
- Drive GRR data collection and analysis, and work with Test Engineers to improve test program stability considering test time reduction trade-offs.
- Support QA and Reliability teams across a range of product qualification requirements.
- Finalize test limits for mass production and define appropriate guard bands based on ATE-to-bench correlation, GRR, HTOL, and PVT characterization results.
- Work with internal teams to support mass production ramp.
Minimum Qualifications
In-depth knowledge of semiconductor manufacturing processes.
Solid understanding of Analog, DC, and power fundamentals.
Strong foundation in statistical data analysis.
Excellent written and verbal communication skills, with the ability to drive alignment across cross-functional teams.
Fluency in English is required.
BS/MS in Electrical Engineering, Computer Engineering, or equivalent is required.
Preferred Qualifications
Ideally several years of experience in semiconductor product engineering.
Experience working with cross-functional teams to define ATE characterization test plans, coordinate data collection, and perform analysis across PVT.
Direct experience with yield management in high-volume manufacturing.
Good understanding of GRR analysis, ATE-to-bench correlation, guard-banding methodologies, and the statistics behind test limit definition.
Familiarity with product and package qualification requirements (HTOL, ESD, latch-up, etc.).
Experience with AI/ML tools and frameworks is a plus.
Ability to set up DOEs to drive root cause of diverse failure mechanisms.
Exposure to analog package technologies is considered a plus.
Exposure to analog test methodologies is a plus.
This role requires occasional international travel.