As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will include:
• Architecting and designing state-of-the-art security features, working closely with Platform Architecture, Design Verification to deliver high performance, area and power efficient RTL Blocks on time
• Integrating security IPs into secure subsystem and ensuring timing, performance and security requirements are met.
• Resolving integration issues across multiple IP blocks and coordinating with IP owners on interface and functionality concerns
• Driving front-end quality flows from RTL to netlist, including hands-on work with Lint, CDC/RDC analysis, UPF development, timing, and Synthesis.
• Leveraging AI-assisted tools to enhance design quality and productivity.

An overview of Secure Enclave is available here: https://support.apple.com/guide/security/the-secure-enclave-sec59b0b31ff/web

Minimum Qualifications
BS in Electrical Engineering, Computer Engineering or a relevant field and 0 years of experience

Preferred Qualifications
Solid RTL design experience using Verilog or SystemVerilog: finite state machines, pipelining, and similar computer-architecture fundamentals.
Strong problems-solving and collaboration skills
Solid understanding of digital design fundamentals including CDC (Clock Domain Crossing), synthesis, timing closure
Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB).
Familiarity with low-power design techniques
Background in cryptography and cryptographic algorithm implementations is a bonus but not must-have